1. Field of the Invention
The present invention relates to a semiconductor device and a control method thereof, and in particular, relates to a semiconductor device containing an internal voltage generating circuit and a control method thereof.
2. Description of Related Art
A semiconductor device such as a DRAM (Dynamic Random Access Memory) may contain a circuit operating based on an internal voltage that is different from an external voltage supplied from outside. In such a semiconductor device, an internal voltage generating circuit that generates an internal voltage based on an external voltage is provided (see Japanese Patent Application Laid-Open Nos. 2008-112507, 2000-306380, H2-156498, and 2004-147458).
An internal voltage generating circuit described in Japanese Patent Application Laid-Open No. 2008-112507 or Japanese Patent Application Laid-Open No. 2000-306380 generates an internal voltage by operating a plurality of parallel-connected stages in parallel. An internal voltage generating circuit described in Japanese Patent Application Laid-Open No. H2-156498 generates an internal voltage by selectively operating a plurality of parallel-connected stages. An internal voltage generating circuit described in Japanese Patent Application Laid-Open No. 2004-147458 reduces a rapid change of voltage by shifting the start timing of operation between a plurality of parallel-connected stages.
The internal voltage generating circuit described in Japanese Patent Application Laid-Open No. 2008-112507 or Japanese Patent Application Laid-Open No. 2000-306380 uses a plurality of oscillator signals with different phases and generates an internal voltage by supplying each of these oscillator signals to the plurality of stages. Thus, the start timing of operation and the stop timing of operation in each stage are shifted by a difference of phase, but the timing serving as a reference for the operation start or operation stop is entirely common. Therefore, when the internal voltage generating circuit is activated or inactivated, the internal voltage may fluctuate sharply, damaging stability of the internal voltage. In the internal voltage generating circuit described in Japanese Patent Application Laid-Open No. 2004-147458, on the contrary, the timing serving as a reference for the operation start is shifted by using an edge counter, but no step is taken for the timing serving as a reference for the operation stop. Therefore, when the internal voltage generating circuit is inactivated, the internal voltage may fluctuate sharply.
The above problems become particularly noticeable in a wide-range semiconductor device in which the range of the available external voltage is wide. The reason therefor is as follows. In a wide-range semiconductor device, it is unavoidable to design an internal voltage generating circuit by assuming a case when the level of the actually used external voltage is the lower limit of the available external voltage. That is, it is necessary to design the voltage supply ability of an internal voltage generating circuit higher in advance. Thus, if the level of the actually used external voltage is, for example, the upper limit of the available external voltage, instead of the lower limit thereof, the voltage supply ability of the internal voltage generating circuit becomes excessive. As a result, the internal voltage may fluctuate due to activation and inactivation of the internal voltage generating circuit. Such a problem cannot be solved by internal voltage generating circuits described in Japanese Patent Application Laid-Open Nos. 2008-112507, 2000-306380, H2-156498, and 2004-147458.